Job openings for verification engineer in bangalore

Experience in Design Verification.

oexperience Developing and Working with Object Oriented Verification Languages (vera, Specman, System Verilog, Vmm, Ovm, Uvm)

oa Solid Understanding of Object-oriented Concepts and Experience Designing Class-based Test Benches

oexcellent Written and Oral Communication Skills

ostrong Debugging Skills

ostrong C/c++, Perl, and Scripting Skills

oexperience with Formal Verification Tools, Hardware Design and Debug, Systemc and other Programming Languages are a Plus.

oexperience Working with Ovm, or Specman E is a Plus

oexperience Working with Emulators, Accelerators and Fpga Based Prototyping a Plus

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